Output device circuit and method to minimize impedance fluctuations during crossover

ABSTRACT

An output driver circuit of the type having two transmission gates, which are preferably CMOS transmission gates, is improved by inserting a variable, and preferably digitally programmable, pulse stretcher in the path of both the high-enable and the low-enable signals that open and close the high-side and low-side transmission gates. The variable delay element of the pulse stretcher can be set to an optimum delay by an &#34;empirical&#34; procedure that entails applying a series of pulses of incrementally varying duration to the output driver circuit, while monitoring the quality of waveform that they produce. A few of these waveforms will be distorted as a result of the impedance mismatch. The variable delay element of the pulse stretcher is then repeatedly adjusted. For each value of variable delay, another series of pulses of incrementally varying duration are again applied to the output of the driver circuit while the quality of the waveforms produced is monitored. The optimum value for the variable delay element setting is the value that most effectively minimizes the distortion in the monitored waveforms. After this empirical procedure has been used to determine one set of optimum timing values, another &#34;inferred&#34; method can then be used to measure the turn on and turn off times that resulted from the empirical method. Thereafter, this inferred method can be used to set the timing on other similar output driver circuits to these same times, without going through the more lengthy empirical procedure again.

This is a continuation of application of Ser. No. 325,263 filed Mar. 17,1989 and now abandoned.

BACKGROUND OF THE INVENTION

This invention relates to the field of output driver or buffer circuits,and more particularly to the field of minimizing crossover impedancefluctuations during state transitions of an output driver circuit havingtwo transmission gates whose active impedances nominally match thecircuit or transmission line being driven.

When testing integrated circuit devices or modules, low-distortion inputwaveforms are required at the input terminals of the device under test(DUT). The input terminals of the DUT and the output driver of thetester are separated by a transmission line which shall be referred toas the tester I/O path. The tester output driver circuit generateswaveforms that travel the tester I/O path and provide stimulus to theinput terminal of the DUT.

U.S. Pat. No. 4,707,620 describes an adjustable impedance driver networkcomprising a plurality of CMOS (complementary metal-oxide semiconductor)transmission gates each of which is separately controlled byprogrammable digital input codes to vary the overall impedance of thenetwork in its conducting state. While this CMOS driver (or buffer) hasthe advantages of an adjustable output impedance, fast rise times thatpermit operation up to 100 MHz or more, and relatively low cost, itsuffers from the disadvantage of not producing a stable impedance duringtransitions between logic states.

FIG. 1 is a simplified schematic diagram of a prior art output drivercircuit on a CMOS integrated circuit (IC), a tester I/O path external tothe IC, and a device under test (DUT). The DUT circuitry may or may not,at any given time, provide a termination resistor to a terminationvoltage. The circuitry of the output driver includes two CMOStransmission gate networks and an associated control logic circuit. Whenan Inhibit signal is asserted (high), both CMOS transmission gatenetworks are held off and the driver is in a high impedance state,effectively disconnected from the tester I/O path. If the driver is notinhibited, a logic "1" on the Data input turns on the upper CMOStransmission gate network and thereby connects the V-high voltage levelto the tester I/O path through the nominal impedance of the CMOStransmission gate. When Data is a logic "0", the lower CMOS transmissiongate network is turned on and the V-low voltage level is connected tothe tester I/O path through the nominal impedance of that CMOStransmission gate.

FIG. 2 is a timing diagram showing how the output impedance of thedriver circuitry may vary during logic state transitions due todifferent propagation delays through the control logic circuitry ofFIG. 1. Slight variations between the transition times of the low-enablesignal and the high-enable signal can lead to intervals of very high (ortoo low) impedance on the output. The control circuit shown in FIG. 1consistently turns off the currently enabled transmission gate beforeturning on the other one, so the impedance fluctuation is always in thehigh direction.

Normally, the impedance of the output driver circuitry is approximatelymatched to the impedance of the tester I/O path. But, during thesetransition intervals with their very high impedance, a serious impedancemismatch occurs and this can cause problems under some circumstances. Inparticular, if a reflected voltage wavefront arrives back at the driverduring one of these periods, the resulting impedance mismatch causes astrong reflection back toward the DUT and the signal quality isdegraded. In other cases, even when the tester I/O path is terminated,those periods when one device has turned off before the other deviceturns on can cause glitches and other aberrant behavior, depending onthe voltage to which the tester I/O path is being terminated.

What is desired is a method and apparatus for minimizing the amount ofimpedance mismatch that occurs during a transition in logic states in anoutput driver circuit having two transmission gates whose activeimpedances nominally match the circuit or transmission line beingdriven.

SUMMARY OF THE INVENTION

The present invention is an improved output driver (buffer) circuit ofthe type having two transmission gates whose active impedances nominallymatch the circuit or transmission line being driven, and a method forusing this circuit to minimize the amount of output impedancefluctuation that occurs during a transition in logic states.

The improvement to the output driver circuit consists of inserting avariable, and preferably digitally programmable, pulse stretchingcircuit in the path of both the high-enable and the low-enable signalsthat open and close the high-side and low-side transmission gates. Apulse stretching circuit, or pulse stretcher, is any circuit that delayspulse edges of one polarity, while not delaying pulse edges of the otherpolarity.

The variable delay element of the pulse stretcher can be set to anoptimum delay by an "empirical" method that entails applying a series ofpulses of incrementally varying duration to the output driver circuit,while monitoring the quality of waveform that they produce. A few ofthese waveforms are distorted as a result of the fact that the initialwavefront sent from the driver was reflected from the DUT end of the I/Opath, and arrived back at the driver during the time of the impedancemismatch. The variable delay element of the pulse stretcher is thenrepeatedly adjusted. For each value of variable delay, another series ofpulses of incrementally varying duration are again applied to the outputof the driver circuit while the quality of the waveforms produced ismonitored. The optimum value for the variable delay element setting isthe value that most effectively minimizes the distortion in themonitored waveforms.

After the empirical procedure has been used to determine one set ofoptimum timing values, an "inferred" method can then be used to measurethe turn on and turn off times that produced the optimum timing values.Thereafter, this inferred method can be used to set the timing on otherdevices to these same times, without going through the more lengthyempirical procedure.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is schematic diagram of a prior art CMOS output driver circuit.

FIG. 2 is a timing diagram illustrating how intervals of impedancemismatch occur.

FIG. 3 is a block diagram of a generalized output driver circuit.

FIG. 4 is a block diagram of a generalized output driver circuitimproved according to the present invention.

FIG. 5 is a schematic diagram of an improved CMOS output driver circuitaccording to the present invention.

FIG. 6 is a timing diagram illustrating part of the calibratingprocedure according to the present invention.

FIG. 7A shows a series of pulses, each having incrementally differingdurations, with distortion present indicating an impedance mismatch.

FIG. 7B shows a series of pulses, each having incrementally differingdurations, with minimum distortion present indicating a minimization ofimpedance mismatch.

FIG. 8A shows how the high-enable and the low-enable turn on points maybe measured using an unterminated output driver pulse.

FIG. 8B shows how the low-enable turn off point may be measured byterminating the driver output with a resistor and disabling thehigh-side transmission gate.

FIG. 8C shows how the high-enable turn off point may be measured byterminating the driver output with a resistor and disabling the low-sidetransmission gate.

DETAILED DESCRIPTION

FIG. 3 is a block diagram of a generalized output driver circuit havinghigh-side and low-side transmission gates whose active impedancesnominally match the impedance of the circuit or transmission line beingdriven. The term "transmission gate", is used herein in its broadestsense and refers to any FET-like or MOS-type device or their functionalequivalents. That is, any device with some nominal active impedancestate and a high impedance state that can be controlled to connect ordisconnect two other circuits from each other through the nominal activeimpedance. In a narrower sense, the term "transmission gate" refers toCMOS transmission gates, which are a type of transmission gate withideal characteristics. In a CMOS transmission gate p-channel andn-channel devices are arranged in parallel, so that the changes in thenominal resistance of the two channels cancel out as the source anddrain voltages approach the control voltages, whereas in a devicerelying on a single channel type the resistance changes significantly asthis occurs. When the narrower definition is intended, the term "CMOStransmission gate" will be used.

Referring to FIG. 3, when a logical "1" appears on the data line, in theabsence of a logical "1" on the inhibit line, the control circuit 2produces an asserted signal condition on the high-enable signal line andan unasserted condition on the low-enable signal line. An assertedsignal condition on the high-enable signal line causes the high-sidetransmission gate 8 to change its impedance from a very high valueapproaching infinity to its nominal active value. The unasserted signalcondition on the low-enable signal line causes the low-side transmissiongate 9 to change its impedance from its nominal active value to a veryhigh value approaching infinity.

Unless the relative timing of the high-enable signal and the low-enablesignal is precisely correct, the transitions in impedance value for thetransmission gates 8,9 will not be occurring at exactly the same time,with the result that the impedance presented to the output varies duringthe transition from one logical value to another.

FIG. 4 shows the generalized output driver circuit of FIG. 3 with avariable pulse stretcher 4,6 inserted in each enable signal path. With aproper selection of delay values for these variable pulse stretchers,the adjusted high-enable and low-enable signals can be made to have theexact timing relationship necessary to minimize the variation in theoutput impedance of the driver circuit during logic state transitions.

FIG. 5 is a schematic diagram of an output driver circuit employing CMOStransmission gates, as shown in FIG. 1, but improved according to thepresent invention, as shown in FIG. 4. Variable pulse stretcher 4 can beseen to comprise NOR gate 3 and variable delay element 5, with thehigh-enable signal from the control circuit 2 applied directly to oneinput of the NOR gate and indirectly to the other input through thevariable delay element. Ideally, the variable delay element is digitallyprogrammable, so as to conveniently lend itself to microprocessorcontrol.

FIG. 6 shows how the application of different values to the programmablevariable delay elements 5 (in FIG. 5) can be used to move thenegative-going edges of the low-enable and high-enable signals tominimize the amplitude and duration of the impedance mismatch. Theimpedance values shown in the bottom half of FIG. 6 are not measureddirectly, but rather are inferred from the presence or absence ofdistortion in the shape of a series of pulses, each having incrementallydiffering durations, as they are monitored at the terminated end (deviceunder test end) of the tester I/O path. This approach has and will bereferred to as the "empirical method".

FIG. 7A shows a series of pulses, each having incrementally differingdurations, with distortion clearly present on some of them indicating animpedance mismatch. If such a series of pulses is examined for each of avariety of pulse stretcher delay values, one of the delay valuesproduces a series of pulses with a minimum of distortion, as shown inFIG. 7B.

Referring now to FIG. 8A, with the tester I/O path unterminated, thesignal level at the output of the driver does not react immediately whenthe low-enable signal causes the low-side CMOS transmission gate to goto its high impedance state. Rather, the signal level reacts when thehigh-enable causes the high-side CMOS transmission gate to go to itsnominal impedance state. Similarly, during the low-going transition, thesignal level at the output of the driver does not react immediately whenthe high-enable signal causes the high-side CMOS transmission gate to goto its high impedance state. Rather, the output signal level reacts whenthe low-enable causes the low-side CMOS transmission gate to go to itsnominal impedance state. Thus, from operation of the output driver withthe tester I/O path unterminated, the high-enable and low-enable turn ontimes can be located in time relative to some convenient referencesignal, such as the Data input to the control circuitry 2.

Referring now to FIG. 8B, with the tester I/O path replaced with aresistor and the high-side CMOS transmission gate temporarily disabled,the location in time of the low-enable turn off can be established. (Ifthe CMOS transmission gate is of the improved type disclosed in U.S.Pat. No. 4,707,620, so that the nominal active resistance can beadjusted, this adjustment capability can be used to set the nominalactive impedance to nearly infinity, thereby, in effect, disabling it.)And, similarly, as shown in FIG. 8C, with the tester I/O path replacedwith a resistor and the low-side CMOS transmission gate temporarilydisabled, the location in time of the high-enable turn off can also beestablished.

Using the technique just described for measuring the turn on and turnoff times of both CMOS transmission gates, which shall be referred to asthe "inferred method", the times for an output driver circuit whosetransition impedance fluctuations have already been minimized accordingto the empirical method described earlier can be measured. With thesetimes established, they can then be used in conjunction with furtherapplication of the inferred method to set the variable delay elements ofother "similar" uncalibrated output drivers without further resort tothe empirical method. By "similar" it is meant that the inferred methodwill only work for output drivers wherein the transmission gatecircuitry was produced by the same process using identical mask sets, sothat the local timing characteristics of the transmission gates are thesame.

While a preferred embodiment of the present invention has been shown anddescribed, it will be apparent to those skilled in the art that manychanges and modifications may be made without departing from theinvention in its broader aspects. The claims that follow are thereforeintended to cover all such changes and modifications as fall within thetrue spirit and scope of the invention.

I claim:
 1. An improved output driver circuit of the type having acontrol circuit for generating a high-enable signal and a low-enablesignal, a high-side transmission gate coupled to the control circuitover a high-enable signal path, and a low-side transmission gate coupledto the control circuit over a low-enable signal path, wherein theimprovement comprises:means coupled between the control circuit and thehigh-side transmission gate in the high-enable signal path for adjustingthe trailing edge of the high-enable signal to produce a stretchedhigh-enable signal for controlling the high-side transmission gate; andmeans coupled between the control circuit and the low-side transmissiongate in the low-enable signal path for adjusting the trailing edge ofthe low-enable signal to produce a stretched low-enable signal forcontrolling the low-side transmission gate.
 2. An improved output drivercircuit as recited in claim 1 wherein the adjusting means each comprisesa two-input NOR gate and a variable delay element, with the respectiveenable signal coupled directly to one input of the NOR gate andindirectly coupled to the other input of the NOR gate through thevariable delay element to produce the respective stretched enable signalat the output of the NOR gate.
 3. An improved output driver circuit asrecited in claim 2 wherein the variable delay element is digitallyprogrammable.
 4. An improved output driver circuit as recited in claim 1wherein the high-side and low-side transmission gates comprise CMOStransmission gates.
 5. A method for minimizing impedance mismatchbetween a transmission line and an output driver circuit coupled todrive the transmission line, wherein the output driver circuit is of thetype having a high-side transmission gate disposed between a high-sidevoltage and an output, and a low-side transmission gate disposed betweena low-side voltage and the output, and a control circuit for generatinga high-enable signal and a low-enable signal, the high-enable signalbeing applied to a first variable pulse stretcher to produce an adjustedhigh-enable signal with a delayed trailing edge and the low-enablesignal being applied to a second variable pulse stretcher to produce anadjusted low-enable signal with a delayed trailing edge, and with theadjusted high-enable signal being coupled to turn on the high-sidetransmission gate and the adjusted low-enable signal being coupled toturn on the low-side transmission gate, the method comprising the stepsof:incrementally varying the delay applied by the first variable pulsestretcher over a first set of delay values; for each incrementallyvaried delay, sending a series of high-going pulses having incrementallyvarying durations through the output driver circuit to drive thetransmission line; for each pulse in the series of high-going pulses,monitoring an amount that a monitored waveform differs from apredetermined waveform; selecting from the first set of delay values asa desired delay value for the first variable pulse stretcher the delayvalue that produced a minimum amount of difference between the resultingwaveform and the predetermined waveform for the series of high-goingpulses; incrementally varying the delay applied by the second variablepulse stretcher over a second set of delay values; for eachincrementally varied delay, sending a series of low-going pulses havingincrementally varying durations through the output driver circuit todrive the transmission line; for each pulse in the series of low-goingpulses, monitoring an amount that a resulting waveform differs from apredetermined waveform; selecting from the second set of delay values asa desired delay value for the second variable pulse stretcher the delayvalue that produced a minimum amount of difference between the resultingwaveform and the predetermined waveform for the series of low-goingpulses.
 6. A method as recited in claim 5 comprising the further stepsof:determining a first timing relationship between a low-enable turn offtime and a high-enable turn on time and a second timing relationshipbetween a high-enable turn off time and a low-enable turn on time, andsetting the desired delay values of other similar output driver circuitsaccording to the first and second determined timing relationships.
 7. Amethod as recited in claim 6 wherein the determining step comprises thesteps of:with the transmission line unterminated locating high-enableand low-enable turn on times relative to a reference signal; with thetransmission line terminated and the high-side transmission gatedisabled locating a low-enable turn off time relative to the referencesignal; with the transmission line terminated and the low-sidetransmission gate disabled locating a high-enable turn off time relativeto the reference signal; and calculating a difference between thelow-enable turn off time and the high-enable turn-on time, thedifference representing the first determined timing relationship; andcalculating a difference between the high-enable turn off time and thelow-enable turn on time, the difference representing the seconddetermined timing relationship.
 8. A method as recited in claim 6wherein the setting step comprises the steps of:with the transmissionline unterminated locating high-enable and low-enable turn on timesrelative to the reference signal; with the transmission line terminatedand the high-side transmission gate disabled selecting a low-enable turnoff time to satisfy the first determined timing relationship; and withthe transmission line terminated and the low-side transmission gatedisabled selecting a high-enable turn off time to satisfy the seconddetermined timing relationship.
 9. A method for minimizing impedancemismatch between a transmission line and a plurality of output drivercircuits, each circuits being coupled to drive the transmission linecircuit when an impedance mismatch between the transmission line and oneof the output driver circuits has previously been minimized, wherein theoutput driver circuits are of the type having a control circuit forgenerating a high-enable signal and low enable signal, a high-sidetransmission gate being coupled to the control circuit via a high-enablesignal path and responsive to the high-enable signal, and a low-sidetransmission gate being coupled to the control circuit via a low-enablesignal path and responsive to the low-enable signal, and having pulsestretcher circuits, each including a variable delay element, disposed inthe high-enable and low-enable signal paths between the control circuitand respective transmission gates, the method comprising the stepsof:determining a first timing relationship between a low-enable turn offtime and a high-enable turn on time and a second timing relationshipbetween a high-enable turn off time and a low-enable turn on time forthe output driver circuit whose impedance mismatch was previouslyminimized, and setting desired delay values of the plurality of outputdriver circuits.
 10. A method as recited in claim 9 wherein thedetermining step comprises the steps of:with the transmission lineunterminated locating high-enable and low-enable turn on times relativeto a reference signal; with the transmission line terminated and thehigh-side transmission gate disabled locating a low-enable turn off timerelative to the reference signal; with the transmission line terminatedand the low-side transmission gate disabled locating a high-enable turnoff time relative to the reference signal; and calculating a differencebetween the low-enable turn off time and the high-enable turn-on time,the difference representing the first determined timing relationship;and calculating a difference between the high-enable turn off time andthe low-enable turn on time, the difference representing the seconddetermined timing relationship.
 11. A method as recited in claim 9wherein the setting step comprises the steps of:with the transmissionline unterminated locating high-enable and low-enable turn on timesrelative to a reference signal; with the transmission line terminatedand the high-side transmission gate disabled selecting a low-enable turnoff time to satisfy the first determined timing relationship; and withthe transmission line terminated and the low-side transmission gatedisabled selecting a high-enable turn off time to satisfy the seconddetermined timing relationship.